Digital processing circuits often require latches for temporarily storing digital signals when transferring such signals between circuits. Such applications include high-speed A/D and D/A converters, high-speed memories, such as RAMs, ROMs, EPROMs, etc., high-speed pipelined logic circuits, and other applications.
Data latches are generally clocked to assure that the data being transferred is reliably stored, and that a coordinated transfer is accomplished without loss of data. In order to ensure that a data latch reliably stores digital signals presented at its input, such digital signal must be held at the latch input for a specified period of time during the input clocking cycle. The state of the digital signal appearing at the input of the latch during the noted period of time can then be reliably latched or stored in a flip-flop circuit internal to the latch. The specified period of time is termed the "hold time". The data is clocked and stored in the latch during such hold time, and thereafter the data on the input line of the latch can be changed without affecting the data stored within the latch.
High-speed data operations are optimized by minimizing the data hold time of the latches. Thus, the faster the data can be latched and stored, the processing of other digital circuits can commence for preparing updated or new inputs to the latches. High-speed CMOS data latches are currently available which operate at speeds up to twenty MHz. Such a latch is disclosed in the article "A CMOS 8-bit High-Speed A/D Converter IC", IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-20, No. 3, p. 775, June, 1985. The disadvantage of such a latch circuit, however, is its extremely long hold time, thus limiting the speed with which the latch may be used with other circuits.
It can be seen that a need exists for an improved high-speed data latch with an extremely short data hold time so that such latch does not present a limitation when used with other high-speed circuits. An additional need exists for a memory sense amplifier data latch in which the hold time is so small that a single clock transition can be utilized to sense data on the data line as well as precharge the data line, thereby reducing the complexity of the clocking schemes in memory support circuits.